Apparatus for detecting edges of input signal to execute signal processing on the basic of edge timings

ABSTRACT

An apparatus for detecting an edge timing of an input signal and operating on the basis of the edge timing while power consumption thereof is reduced. The apparatus includes an edge detecting circuit that detects edges of an input signal to generate an edge timing representing signal representative of edge timings of the edges, a signal processing circuit responsive to the edge timing representing signal. The edge detection circuit outputs an enable signal to enable the signal processing circuit to operate when the edge detection circuit finds one of the edges. The signal processing circuit executes a signal processing of the edge timing representing signal in response to the enable signal.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to an apparatus. More particularly,the present invention relates to an apparatus for detecting edges of aninput signal to executes signal processing on the basis of edge timings.

[0003] 2. Description of the Related Art

[0004] Edge detecting circuits are widely used for various signalprocessing. An edge detecting circuit is disclosed in Japanese Laid OpenPatent Application (JP-A-2001 136157). The entire disclosure of thecorresponding U.S. patent application Ser. No. 09/699,245, filed Oct.27, 2000 is hereby incorporated herein in its entirety by reference. Theedge detecting circuit is used in a clock signal reproducing apparatus.The clock signal reproducing apparatus is composed of a detectingcircuit and a clock signal outputting circuit. The detecting circuitdetects edge timings of an input signal at which the input signal isinverted. The detecting circuit quantizes the detected edge timings to apredetermined number of states. The clock signal outputting circuitoutputs an outputted clock signal. A phase of the outputted clock signalis established based on the edge timings.

[0005] Another edge detecting circuit for surely detecting edges ofsignals is disclosed in Japanese Laid Open Patent Application(JP-A-Heisei 1-260915). As shown in FIG. 1, the conventional apparatusincludes flip-flop circuits 101-104, inverters 105, 106, delay circuits107-110, XOR gates 111-114, an OR gate 115 and an address decoder 116.The conventional apparatus detects that address signals 120, 121 arechanged from the High level to the Low level or from the Low level tothe High level.

[0006] When the address signal 120 is changed from the Low level to theHigh level as shown in FIG. 2, the flip-flop circuit 101 detects thechange to generate an output pulse. Next, when the address signal 120 ischanged from the High level to the Low level, the flip-flop circuit 102detects the change. In the conventional edge detecting circuit, even ifthe change to the High level from the Low level is done in the timeshorter than the predetermined delay time T_(W), a sure edge detectionsignal is inputted to an enable terminal of the address decoder 116without any separation of the output pulse.

[0007] However, the conventional edge detecting circuit does not outputa signal indicating edge timings of the address signals 120, 121. Theconventional edge detecting circuit merely detects that the addresssignals 120, 121 are changed from the High level to the Low level, orfrom the Low level to the High level, and only sets the address decoder116 enable.

[0008] Also, a synchronizing circuit including an edge detecting circuitis disclosed in Japanese Laid Open Patent Application (JP-A-Heisei4-13325). The synchronizing circuit receives a data signal, synchronizesan interior clock signal with the data signal, and samples the datasignal with the synchronized clock signal. In detail, the synchronizingcircuit includes a data signal edge detecting circuit, a clock signaledge detecting circuit, a synchronization judging circuit, and a clocksignal selecting circuit. The data signal edge detecting circuit outputsa data signal edge detection pulse when detecting an edge of the datasignal. The clock signal edge detecting circuit outputs a clock signaledge detection pulse when detecting an edge of the clock signal. Thesynchronization judging circuit superposes the data signal edgedetection pulse and the clock signal edge detection pulse to output anasynchronous state detection pulse. The clock signal is responsive toasynchronous state detection pulse for selecting one of clock signalshaving different phases to output it as the interior clock signal.However, the edge timing of the data signal is not detected in thesynchronizing circuit and the operation of the synchronizing circuit isnot based on the edge timing.

SUMMARY OF THE INVENTION

[0009] An object of the present invention is to provide an apparatus fordetecting an edge timing and operating on the basis of the edge timingwhile power consumption thereof is reduced.

[0010] Another object of the present invention is to provide anapparatus for detecting an edge timing and operating on the basis of theedge timing while the operation thereof is stabilized.

[0011] In order to achieve an aspect of the present invention, anapparatus includes an edge detecting circuit that detects edges of aninput signal to generate an edge timing representing signalrepresentative of edge timings of the edges, a signal processing circuitresponsive to the edge timing representing signal. The edge detectioncircuit outputs an enable signal to enable the signal processing circuitto operate when the edge detection circuit finds one of the edges. Thesignal processing circuit executes a signal processing of the edgetiming representing signal in response to the enable signal.

[0012] The edge detecting circuit preferably quantizes the edge timingsto represent the edge timings in the edge timing representing signal.

[0013] The enable signal preferably consists of rectangular pulseshaving a pulse width larger than a predetermined value.

[0014] The edge detection circuit preferably detects the edges insynchronization with a clock signal, and the pulse width is larger thana cycle of the clock signal.

[0015] The edge detection circuit preferably generates the enable signalbased on the edge timing representing signal.

[0016] The edge detection circuit preferably changes a state of the edgetiming representing signal is changed only when the edge detectiondetects the edges.

[0017] The edge detecting circuit preferably includes a plurality ofsampling circuits each of which is responsive to one of clock signalsfor sampling the input signal in synchronization with the one of theclock signals to generate a sample signal, the clock signals havingdifferent phases each other, and an edge timing determining circuitgenerates the edge timing representing signal based on the samplesignals received from the plurality of sampling circuits, the edgetiming determining circuit determining the edge timings on the basis ofwhether or not two of the sample signals indicate different values.

[0018] In order to achieve another aspect of the present invention, aclock signal reproducing circuit includes an edge detecting circuitwhich detects edges of an input signal to generate an edge timingrepresenting signal representative of edge timings of the edges, a clocksignal outputting circuit responsive to the edge timing representingsignal for generating another clock signal synchronized with the inputsignal. The edge detection circuit outputs an enable signal to enablethe clock signal outputting circuit to operate when the edge detectioncircuit finds one of the edges.

[0019] The clock signal outputting circuit preferably selects one of aplurality of clock signals having different phases each other on thebasis of the edge timing representing signal and output the one of theplurality of clock signals as the another clock signal.

[0020] In the case when the edges have a present edge which is latest ofthe edges, and a past edge detected before the present edge, the clocksignal outputting circuit preferably includes a memorizing circuitmemorizing a past edge timing of the past edge, the another clock signalis outputted on the basis of edge timings of the present edge and thepast edge.

[0021] In order to achieve still another aspect of the presentinvention, a signal reproducing circuit includes an edge detectingcircuit which detects edges of an input signal to generate an edgetiming representing signal representative of edge timings of the edges,a clock signal outputting circuit responsive to the edge timingrepresenting signal for generating another clock signal synchronizedwith the input signal, and a reproduced signal outputting circuitsampling the input signal with the another clock signal to output areproduced signal. The edge detection circuit outputs an enable signalto enable the clock signal outputting circuit to operate when the edgedetection circuit finds one of the edges.

[0022] In order to achieve yet still aspect of the present invention, amethod of operating an apparatus includes:

[0023] detecting edges of an input signal;

[0024] outputting an edge timing representing signal representative ofedge timings of the edges;

[0025] outputting an enable signal when one of the edges is detected;and

[0026] enabling a circuit to operate in response to the edge timingrepresenting signal.

[0027] The circuit preferably outputs a clock signal synchronized withthe input signal on the basis of the edge timings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0028]FIG. 1 shows a configuration of a conventional edge detectioncircuit;

[0029]FIG. 2 is a timing chart showing an operation of the conventionaledge detection circuit;

[0030]FIG. 3 shows a configuration of an apparatus of a first embodimentaccording to the present invention;

[0031]FIG. 4 shows a configuration of a sampling circuit 1;

[0032]FIG. 5 shows a configuration of a leading edge position detectioncircuit 2 ₁;

[0033]FIG. 6 shows a configuration of a trailing edge position detectioncircuit 2 ₂;

[0034]FIG. 7 is a timing chart showing the operations of the samplingcircuit 1, the leading edge position detection circuit 2 ₁ and thetrailing edge position detection circuit 2 ₂;

[0035]FIG. 8 shows the configurations of an optimized leading edgeposition calculator 4 ₁ and an optimized trailing edge positioncalculator 4 ₂;

[0036]FIG. 9 shows a configuration of a second embodiment according tothe present invention;

[0037]FIG. 10 shows a configuration of a leading edge position detectioncircuit 7 ₁; and

[0038]FIG. 11 shows a configuration of a trailing edge positiondetection circuit 7 ₂.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0039] Embodiments according to the present invention will be describedbelow with reference to the attached drawings.

First Embodiment

[0040] An apparatus in a first embodiment is a clock signal reproducingapparatus. The apparatus generates a clock signal synchronous with aninput signal which has waveform thereof distorted through acommunication link. The apparatus also samples the input signal at theclock signal, and reproduces the waveform of the input signal. Theconfiguration of the apparatus will be described below.

[0041]FIG. 3 shows the apparatus in the first embodiment. The apparatusincludes a sampling circuit 1, a leading edge timing detector 2 ₁ and atrailing edge timing detector 2 ₂.

[0042] The sampling circuit 1 is triggered by n clock signalsCLK₀-CLK_(n−1) having different phases to sample an input signal a. Inthe embodiment, n=8. The sampling circuit 1 outputs sample data signalsb₀-b_(n−1) which is representative of the data of input signal a andsynchronous to the clock signals CLK₀-CLK_(n−1).

[0043] The leading edge timing detector 2 ₁ detects a leading edgetiming of the input signal a, on the basis of the sample data signalsb₀-b_(n−1) to generate leading edge timing signals c₀-c_(n−1) indicativeof the detected leading edge timing. Moreover, the leading edge timingdetector 2 ₁ detects an leading edge of the input signal a on the basisof the sample data signals b₀-b_(n−1) to set an edge detection signal e₁to the High level for a certain time.

[0044] The trailing edge timing detector 2 ₂ carries out the operationsimilar to that of the leading edge timing detector 2 ₁ except theoperation for detecting the trailing edge timing of the input signal a.The trailing edge timing detector 2 ₂ detects the trailing edge timingof the input signal a on the basis of the sample data signals b₀-b_(n−1)to generate leading edge timing signals d₀-d_(n−1) indicative of thedetected leading edge timing. Moreover, the leading edge timing detector2 ₁ detects the trailing edge of the input signal a to set an edgedetection signal e₂ to the High level for a certain time.

[0045] The leading edge timing signals c₀-c_(n−1) the trailing edgetiming signals d₀-d_(n−1) and the edge detection signals e₁, e₂ areoutputted to a signal reproducing circuit 3.

[0046] The signal reproducing circuit 3 is enabled by the edge detectionsignals e₁, and captures the leading edge timing signals c₀-c_(n−1) whenthe edge detection signal e₁ is changed from the Low level to the Highlevel. Moreover, the signal reproducing circuit 3 is enabled by the edgedetection signal e₂, and captures the trailing edge timing signalsd₀-d_(n−1) when the edge detection signal e₂ is changed from the Lowlevel to the High level. The signal reproducing circuit 3 selects aclock signal which is in the most synchronous state with the inputsignal a from the clock signals CLK₀-CLK_(n−1) on the basis of theleading edge timing of the input signal a indicated by the leading edgetiming signals c₀-c_(n−1) and the trailing edge timing of the inputsignal a indicated by the trailing edge timing signals d₀-d_(n−1). Thenthe signal reproducing circuit 3 outputs the selected clock signal as aselection clock signal f. Moreover, the signal reproducing circuit 3outputs one of the sample data signals b₀ to b_(n−1) as a datareproduction signal g, which corresponds to a signal generated bysampling the input signal a with the selection clock signal f.

[0047] In the apparatus, the signal reproducing circuit 3 is enabled bythe edge detection signals e₁, e₂ when the leading edge and the trailingedge of the input signal a are detected. When the leading edge and thetrailing edge in the input signal a are detected, the signal reproducingcircuit 3 is enabled to operate. When the leading edge and the trailingedge in the input signal a are not detected, the signal reproducingcircuit 3 does not operate. This suppresses the consumption of theelectric power of the apparatus.

[0048] The apparatus of the embodiment will be described below indetail.

[0049] The clock signals CLK₀ to CLK_(n−1), are inputted to the samplingcircuit 1. The clock signals CLK₀ to CLK_(n−1) have the same cycle T andthe same pulse width T_(W) while their phases are different from eachother. The phase of the clock signal CLK₁ is delayed by 2πi/n from theclock signals CLK₀. Here, i is an integer between 0 and n−1. Thesampling circuit 1 uses the clock signals CLK₀-CLK_(n−1) for samplingthe input signals a.

[0050] In this specification, the phase is defined as 0 at a time whenthe clock signal CLK₀ rises from the Low level to the High level.According to this definition, the clock signal CLK_(i), whose phase isdelayed by 2πi/n from the clock signal CLK₀, is pulled from the Lowlevel up to the High level at a time when the phase is at 2πi/n.

[0051]FIG. 4 shows the configuration of the sampling circuit 1. Thesampling circuit 1 includes D-flip-flops 1 ₀-1 _(n−1). The input signala is inputted to each of the D-flip-flops 1 ₀-1 _(n−1). Moreover, theclock signals CLK₀ to CLK_(n−1) are inputted to the D-flip-flops 1 ₀-1_(n−1), respectively. The D-flip-flops 1 ₀-1 _(n−1) respectively use theclock signals CLK₀-CLK_(n−1) for sampling the input signal a, and thenoutput the sample signals b₀-b_(n−1), respectively. The sample signalsb₀-b_(n−1) are outputted to the leading edge timing detector 2 ₁ and thetrailing edge timing detector 2 ₂.

[0052] As mentioned above, the leading edge timing detector 2 ₁ detectsthe leading edge timings of the input signal a, on the basis of thesample signals b₀ to b_(n−1).

[0053] The leading edge timings detected by the leading edge timingdetector 2 ₁ are quantized to n states and represented by the integerbetween 0 and n−1. Here, the fact that the leading edge timing of theinput signal a is at i implies that the input signal a is pulled up tothe High level between a time when the phase is at 2πi/n and a time whenthe phase is at 2π(i+1)/n. Here, i is the integer between 0 and n−1. Forexample, let us suppose a case of i=0. The fact that the leading edgetiming is at 0 implies that the input signal a rises between a time whenthe phase is at 0 and a time when the phase is at 2π/n. Similarly, thefact that the leading edge timing is at 1 implies that the input signala rises between a time when the phase is at 2π/n and a time when thephase is at 2π×2/n. Here, the fact that the phase is at 2π×n/n isequivalent to the fact that the phase is at 0. That is, the fact thatthe leading edge timing is at n−1 implies that the input signal a risesbetween a time when the phase is at 2π×n−1/n and a time when the phaseis at 0.

[0054] The state that the leading edge timing signal c₁ is at the Highlevel indicates the leading edge timing is at i. Here, i is the integerbetween 0 and n−1. That is, the leading edge timing signals c₀-c_(n−1)outputted by the leading edge timing detector 2 ₁ indicate the leadingedge timing of the input signal a. The leading edge timing signalsc₀-c_(n−1) are allowed to have a state that all of them are at the Lowlevel or a state that only one of them is at the High level.

[0055]FIG. 5 shows the leading edge timing detector 2 ₁ for generatingthe leading edge timing signals c₀-c_(n−1). The leading edge timingdetector 2 ₁ is provided with AND gates 21 ₀-21 _(n−1), D-flip-flops 22₀-22 _(n−1), an OR gate 23, and inverters 24 ₁, 24 ₂.

[0056] The sample signal b_(i+1) and an inverse of the sample signalb_(i) are inputted to the AND gate 21 _(i). Here, i is the integerbetween 0 and n−1. For example, for i being 0, the sample signal b₁ andthe inverse of the sample signal b₀ are inputted to the AND gate 21 ₀.However, it should be understood that the sample signal b_(n) means thesample signal b₀. That is, the sample signal b₀ and the inverse of thesample signal b_(n−1) are inputted to the AND gate 21 _(n−1). The outputof the AND gate 21 ₁ becomes at the High level when the input signal arises from the Low level to the High level between a time when the phaseis at 2πi/n and a time when the phase is at 2π(i+1)/n. The outputs ofthe AND gates 21 ₀-21 _(n−1) are connected to data terminals D of theD-flip-flops 22 ₀-22 _(n−1), respectively.

[0057] The clock signals CLK₀-CLK_(n−1) are inputted to clock terminalsCLK of the D-flip-flops 22 ₀-22 _(n−1), respectively. The D-flip-flops22 ₀-22 _(n−1) respectively latch the outputs the AND gates 21 ₀-21_(n−1) in synchronization with the leading edge of the clock signalsCLK₀ to CLK_(n−1), respectively.

[0058] Each of the leading edge timing signals c₀-c_(n−1) is outputtedfrom an output terminal Q of each of the D-flip-flops 22 ₀ to 22 _(n−1).The leading edge timing signal c_(i) is pulled up to the High level whenthe input signal a is pulled up to the High level between a time whenthe phase becomes at 2πi/n and a time when the phase becomes at2π(i+1)/n.

[0059] The output terminals Q of the D-flip-flops 22 ₀-22 _(n−1) areconnected to an input of the OR gate 23. An output of the OR gate 23 isconnected to an input of the inverter 24 ₁. An output of the inverter 24₁ is connected to an input of the inverter 24 ₂. An edge detectionsignal e₁ is outputted from an output of the inverter 24 ₂. The edgedetection signal e₁ is pulled up to the High level when any one of theleading edge timing signals c₀-c_(n−1) is at the High level. That is,the edge detection signal e₁ indicates that the input signal a is pulledup to the High level.

[0060] On the other hand, the trailing edge timing detector 2 ₂ detectsthe trailing edge timings of the input signal a on the basis of thesample signals b₀-b_(n−1). The trailing edge timings are also quantizedto n states and represented by the integer between 0 and n−1. The factthat the trailing edge timing of the input signal a is at i implies thatthe input signal a trails between a time when the phase is at 2πi/n anda time when the phase is at 2π(i+1)/n. The fact that the leading edgetiming is at i is indicated by the fact that the leading edge timingsignal d_(i) is at the High level.

[0061]FIG. 6 shows the configuration of the trailing edge timingdetector 2 ₂ for generating the trailing edge timing signals d₀-d_(n−1).The trailing edge timing detector 2 ₂ has the configuration similar tothat of the leading edge timing detector 2 ₁. The trailing edge timingdetector 2 ₂ includes AND gates 25 ₀-25 _(n−1), D-flip-flops 26 ₀-26_(n−1), an OR gate 27 and inverters 28 ₁, 28 ₂.

[0062] The sample signals b_(i) and an inverse of the sample signalb_(n+1) are inputted to the AND gates 25 ₁. Here, i is the integerbetween 0 and n−1. For example, in a case of i=0, the sample signal b₀and the inverse of the sample signal b₁ are inputted to the AND gate 25₀. It should be understood that the sample signal b_(n) means the samplesignal b₀. That is, the sample signal b_(n−1) and the inverse of thesample signal b₀ are inputted to the AND gate 25 _(n−1). The output ofthe AND gate 25 _(i) is pulled up to the High level when the inputsignal a is pulled down from the High level to the Low level between atime when the phase is at 2πi/n and a time when the phase is at2π(i+1)/n. The outputs of the AND gates 25 ₀-25 _(n−1) are connected todata terminals D of the D-flip-flops 26 ₀-26 _(n−1), respectively.

[0063] The D-flip-flops 26 ₀-26 _(n−1) respectively latch the outputs ofthe AND gates 25 ₀-25 _(n−1) to output the trailing edge timing signalsd₀-d_(n−1) respectively, in synchronization with the leading edge of theclock signals CLK₀ to CLK_(n−1), respectively.

[0064] The trailing edge timing signals d₀-d_(n−1) are respectivelyoutputted from the output terminals Q of the D-flip-flops 26 ₀-26_(n−1). The trailing edge timing signal d_(i) among the trailing edgetiming signals d₀-d_(n−1) is pulled up to the High level when the inputsignal a is pulled down from the High level to the Low level between atime when the phase becomes at 2πi/n and a time when the phase becomesat 2π(i+1)/n.

[0065] The output terminals Q of the D-flip-flops 26 ₀-26 _(n−1) areconnected to an input of the OR gate 27. An output of the OR gate 27 isconnected to an input of the inverter 28 ₁. An output of the inverter 28₁ is connected to an input of the inverter 28 ₂. An edge detectionsignal e₂ is outputted from an output of the inverter 28 ₂. The edgedetection signal e₂ becomes at the High level while any one of thetrailing edge timing signals d₀-d_(n−1) becomes at the High level. Thatis, the edge detection signal e₂ indicates that the input signal a ispulled down from the Low level to the High level.

[0066] The operations of the sampling circuit 1, the leading edge timingdetector 2 ₁ and the trailing edge timing detector 2 ₂ will be describedbelow with reference to FIG. 7. In FIG. 7, n is assumed to be 8,therefore the clock signals CLK₀ to CLK_(n−1) are noted as the clocksignals CLK₀ to CLK₇. The sample signals b₀-b_(n−1), the leading edgetiming signals c₀-c_(n−1) and the trailing edge timing signalsd₀-d_(n−1) are similarly noted as the sample signals b₀-b₇, the leadingedge timing signals c₀-c₇ and the trailing edge timing signals d₀-d₇,respectively.

[0067] At a time t<t₁, the input signal a is at the Low level. All ofthe sample signals b₀-b₇ are at the Low level. While t<t₁, the inputsignal a does not have both the leading edge and the trailing edge.Thus, the leading edge timing signals c₀-c₇, the trailing edge timingsignals d₀-d₇ and the edge detection signals e₁, e₂ are all kept at theLow level.

[0068] At the time t₁, the input signal a rises from the Low level tothe High level. The time t₁ is the time between a time when the clocksignal CLK₇ rises and a time when the clock signal CLK₀ rises. That is,the time t₁ is the time between a time when the phase is at2π×7/8(=2π(n−1)/n) and a time when the phase is at 0. The leading edgetiming of the input signal a is detected as 7(=n−1) by the samplingcircuit 1 and the leading edge timing detector 2 ₁. The process of thedetection will be described below.

[0069] The sampling circuit 1 samples the input signal a for each riseof the clock signals CLK₀-CLK₇ to output the sample signals b₀-b₇. Thesample signals b₀-b₇ is pulled up from the Low level to the High levelfor rises of the clock signals CLK₀-CLK₇, respectively.

[0070] Whether the leading edge timing signals c₀-c_(n−1) become at theHigh level or the Low level is determined for each rise of the clocksignals CLK₀-CLK₇. In detail, whether the leading edge timing signalc_(i) becomes at the High level or the Low level after the rise of theclock signal CLK_(i) is determined on the basis of the sample signalsb_(i), b_(i+1) immediately before the rise of the clock signal CLK_(i).Here, i is the integer between 0 and 7(=n−1).

[0071] Immediately before the rise of the clock signal CLK₀, the samplesignals b₀, b₁ are both at the Low level. The leading edge timing signalc₀ indicates the AND of an inverse of the sample signal b₀ and thesample signal b₁, and After the clock signal CLK₀ is pulled up to theHigh level, the leading edge timing signal c₀ is kept at the Low level.

[0072] Similarly, the leading edge timing signals c₁-c₆ are kept at theLow level after the rises of the respective clock signals CLK₁ to CLK₆.

[0073] On the other hand, immediately before the rise of the clocksignal CLK₇, the sample signals b₇, b₀ are at the Low level and the Highlevel, respectively. The leading edge timing signal c₇ indicates the ANDof the sample signal b₀ and an inverse of the sample signal b₇. Thus,the leading edge timing signal c₇ is changed from the Low level to theHigh level at the time of the rise of the clock signal CLK₇.

[0074] In this way, the leading edge timing signals c₀-c₆ become at theLow level, and the leading edge timing signal c₇ becomes at the Highlevel. This implies that the leading edge timing of the input signal ais detected as 7. In this way, the leading edge timing of the inputsignal a is detected as 7(=n−1) by the sampling circuit 1 and theleading edge timing detector 2 ₁.

[0075] The data detection signal e₁, which indicates the OR of theleading edge timing signals c₀-c₇, is pulled up to the High level, inresponse to the pull-up of the leading edge timing signal c₇. The timingwhen the data detection signal e₁ is pulled up to the High level isdelayed by a certain time. This delay time is caused by the OR gate 23and the inverters 24 ₁, 24 ₂ shown in FIG. 5. The inverters 24 ₁, 24 ₂are used for generating the delay time.

[0076] The delay time optimizes the timing when the data detectionsignal e₁ is pulled up to the High level for the capture of the leadingedge timing signals c₀-c₇. As described later, the signal reproducingcircuit 3 captures the leading edge timing signals c₀-c₇ when the datadetection signal e₁ is changed to the High level. The delay in the datadetection signal e₁ ensures the capture of the leading edge timingsignals c₀-c₇.

[0077] The data detection signal e₁ is designed not to return to the Lowlevel within at least a time shorter than the period T of the clocksignals CLK₀ to CLK₇ once the data detection signal e₁ is pulled up tothe High level. That is, a pulse width of a rectangular pulse containedin the data detection signal e₁ is always equal to or longer than theperiod T of the clock signals CLK₀ to CLK₇. The reason is as follows.The leading edge timing signals c₀-c₇ on which the data detection signale₁ is generated, are never changed to the Low level within the timeequal to the period T of the clock signals CLK₀-CLK₇, once the leadingedge timing signals c₀-c₇ are changed to the High level. The states ofthe leading edge timing signals c₀-c₇ are changed only for therespective rises of the clock signals CLK₀ to CLK₇. Thus, once theleading edge timing signals c₀-c₇ are changed to the High level, theleading edge timing signals c₀-c₇ are never pulled down to the Low levelwithin the time shorter than the period T of the clock signals CLK₀ toCLK₇.

[0078] The pulse width equal to or longer than the period T of the clocksignals CLK₀-CLK₇ contributes to the stable operation of the apparatusin the embodiment.

[0079] As shown in FIG. 7, it is assumed that the input signal a, whichrises from the Low level to the High level at the time t₁, is pulleddown to the Low level at a time t₂. The time t₂ is the time between thetime when the clock signal CLK₇ rises and the time when the clock signalCLK₀ rises. That is, the time t₂ is the time between the time when thephase is at 2π×7/8(=2π(n−1)/n) and the time when the phase is at 0. Thetrailing edge timing of the input signal a is detected as 7(=n−1) by thesampling circuit 1 and the trailing edge timing detector 2 ₂. Theprocess of the detection of the trailing edge timing is equal to theabove-mentioned process in which the leading edge timing of the inputsignal a is detected as 7(=n−1).

[0080] The trailing edge timing detector 2 ₂ keeps the trailing edgetiming signals d₀-d₆ at the Low level, and pulls the trailing edgetiming signal d₇ up to the High level when the clock signal CLK₇ rises.That is, the trailing edge timing detector 2 ₂ detects the trailing edgetiming of the input signal a as 7(=n−1).

[0081] Moreover, the trailing edge timing detector 2 ₂ pulls up a datadetection signal e₂ to the High level at a timing that is delayed by acertain delay time from a timing when the trailing edge timing signal d₇is changed to the High level. The pulse width of the data detectionsignal e₂ is equal to or longer than the period T of the clock signalsCLK₀ to CLK₇ from the same reason of the data detection signal e₁.

[0082] The leading edge timing signals c₀-c_(n−1), the edge detectionsignal e₁, the trailing edge timing signals d₀-d_(n−1), and the edgedetection signal e₂ are inputted to the signal reproducing circuit 3.

[0083] As shown in FIG. 3, the signal reproducing circuit 3 includes amost likely leading edge timing calculator 4 ₁, a most likely trailingedge timing calculator 4 ₂, a clock selection circuit 5 and an outputcircuit 6. The most likely leading edge timing calculator 4 ₁ includesan edge timing comparator 41 ₁ and an edge memory circuit 42 ₁. The mostlikely trailing edge timing calculator 4 ₂ includes an edge timingcomparator 41 ₂ and an edge memory circuit 42 ₂.

[0084] The most likely leading edge timing calculator 4 ₁ determines themost likely edge timing which is most likely for the leading edge timingof the input signal a, on the basis of the latest leading edge timingdetected by the leading edge timing detector 2 ₁.

[0085] The latest leading edge timing detected by the leading edgetiming detector 2 ₁ is easily affected by noise and jitter on the inputsignal a. Even if the leading edge timing detector 2 ₁ detects the rapidchange in the leading edge timing, it may result from the noise and thejitter.

[0086] In order to reduce the influence of the noise and the jitter, themost likely leading edge timing calculator 4 ₁ carries out the followingoperation. The most likely leading edge timing of the input signal a isstored in the edge memory circuit 42 ₁. The edge timing comparator 41 ₁compares the stored most likely leading edge timing with the latestleading edge timing detected by the leading edge timing detector 2 ₁.Then, the most likely leading edge timing is gradually adjusted. Themost likely leading edge timing is sent to the clock selection circuit 5by using a most likely leading edge timing signal h₁.

[0087] The most likely leading edge timing calculator 4 ₁ determines themost likely leading edge timing only when the edge detection signal e₁is changed from the Low level to the High level. That is, the mostlikely leading edge timing calculator 4 ₁ determines the most likelyleading edge timing only when the leading edge is detected from theinput signal a. Such the operation suppresses the consumption of theelectric power in the most likely leading edge timing calculator 4 ₁.

[0088]FIG. 8 shows the configuration of the most likely leading edgetiming calculator 4 ₁. As mentioned above, the most likely leading edgetiming calculator 4 ₁ includes the edge timing comparator 41 ₁ and theedge timing memorizing circuit 42 ₁. The edge timing comparator 41 ₁includes a comparator 43 ₁, an addition circuit 44 ₁, a register 45 ₁and a most likely edge timing adjusting circuit 46 ₁.

[0089] As mentioned above, the edge timing memorizing circuit 42 ₁stores the most likely leading edge timing. The most likely leading edgetiming is also quantized to n states in the same way that the leadingedge timing detected by the leading edge timing detector 2 ₁ isquantized. The most likely leading edge timing is represented by aninteger between 0 and n−1.

[0090] The register 45 ₁ stores an integer value C. The integer value Cis deviated larger apart from 0 as a period while the most likelyleading edge timing and the detected leading edge timing are differentfrom each other is longer. A positive or negative value of the integervalue C indicates whether the detected leading edge timing is temporallylocated before or after the most likely leading edge timing. The integervalue C is referred when the most likely leading edge timing isadjusted.

[0091] The leading edge timing signals c₀-c_(n−1) indicative of theleading edge timing detected by the leading edge timing detector 2 ₁ anda most likely leading edge timing signal j₁ indicative of the mostlikely leading edge timing are inputted to the comparator 43 ₁. Thecomparator 43 ₁ compares the leading edge timing with the most likelyleading edge timing.

[0092] The comparator 43 ₁ outputs a comparison output value A on thebasis of the compared result. When the leading edge timing is defined asi₁ and the most likely leading edge timing is defined as i₂, thecomparison output value A is determined as follows. If i₁<i₂, thecomparator 43 ₁ outputs −1 as the comparison output value A. If i₁=i₂,the comparator 43 ₁ outputs 0 as the comparison output value A. And, ifi₁>i₂, the comparator 43 ₁ outputs +1 as the comparison output value A.

[0093] The addition circuit 44 ₁ adds the comparison output value A andthe integer value C held by the register 45 ₁ to output an additionvalue B to the register 45 ₁. The register 45 ₁ captures the additionvalue B to replace the integer value C held therein to the additionvalue B when the edge detection signal e₁ is pulled up to the Highlevel. The register 45 ₁ outputs the integer value C to the most likelyedge timing adjusting circuit 46 ₁.

[0094] The most likely edge timing adjusting circuit 46 ₁ outputs anadjustment instruction signal k₁ for instructing to adjust the mostlikely leading edge timing to the edge timing memorizing circuit 42 ₁ inresponse to the integer value C. When the integer value C reaches apredetermined upper limit, the most likely edge timing adjusting circuit46 ₁ outputs an adjustment instruction signal k₁ for instructing toincrease the most likely leading edge timing by 1 to the edge timingmemorizing circuit 42 ₁. Also, when the integer value C reaches apredetermined lower limit, the most likely edge timing adjusting circuit46 ₁ outputs the adjustment instruction signal k₁ for instructing todecrease the most likely leading edge timing by 1.

[0095] The edge timing memorizing circuit 42 ₁ increase or decrease toadjust the most likely leading edge timing stored therein on the basisof the adjustment instruction signal k₁.

[0096] From the above-mentioned processes, the most likely leading edgetiming calculator 4 ₁ determines the most likely leading edge of theinput signal a, while reducing the influence of the noise and the jitterof the input signal a.

[0097] Also, the most likely trailing edge timing calculator 4 ₂determines the most likely trailing edge timing which is most likely forthe trailing edge timing of the input signal a on the basis of thelatest trailing edge timing detected by the trailing edge timingdetector 2 ₂.

[0098] The most likely trailing edge timing is also quantized to nstates in the same way that the trailing edge timing detected by thetrailing edge timing detector 2 ₂ is quantized, and represented by theinteger between 0 and n−1.

[0099] The most likely trailing edge timing calculator 4 ₂ carries outthe following operation. The most likely trailing edge timing is storedin the edge timing memorizing circuit 42 ₂. The edge comparator 43 ₂compares the most likely trailing edge timing with the latest trailingedge timing detected by the trailing edge timing detector 2 ₂. The mostlikely trailing edge timing is gradually adjusted.

[0100] The most likely trailing edge timing calculator 4 ₂ includes anedge timing comparator 41 ₂ and an edge timing memorizing circuit 42 ₂,as shown in FIG. 8. The edge timing comparator 41 ₂ includes acomparator 43 ₂, an addition circuit 44 ₂, a register 45 ₂ and an mostlikely edge timing adjusting circuit 46 ₂. As shown in FIG. 8, thecircuit configuration of the most likely trailing edge timing calculator4 ₂ is identical to that of the most likely leading edge timingcalculator 4 ₁ except for the signals which are inputted to andoutputted from the most likely trailing edge timing calculator 4 ₂.Also, the operation of the most likely trailing edge timing calculator 4₂ is identical to that of the most likely leading edge timing calculator4 ₁ except for the signals which are inputted to and outputted from themost likely trailing edge timing calculator 4 ₂. Instead of the input ofthe leading edge timing signals c₀-c_(n−1), the trailing edge timingsignals d₀-d_(n−1) are inputted to the most likely trailing edge timingcalculator 4 ₂. The most likely trailing edge timing calculator 4 ₂adjusts the most likely trailing edge timing stored in the edge timingmemorizing circuit 42 ₂, on the basis of the trailing edge timingsignals d₀-d_(n−1).

[0101] The most likely leading edge timing and the most likely trailingedge timing, which are stored in the edge timing memory circuits 42 ₁,42 ₂, respectively, are sent to the clock selection circuit 5 on themost likely leading edge timing signal h₁ and the most likely trailingedge timing signal h₂, respectively.

[0102] The clock selection circuit 5 selects the most suitable one forthe sampling operation of the input signal a, from among the clocksignals CLK₀-CLK_(n−1) on the basis of the most likely leading edgetiming and the most likely trailing edge timing. The clock selectioncircuit 5 selects the one clock signal from the clock signalsCLK₀-CLK_(n−1) such that the leading edge timing of the selected clocksignal is the closest to the middle between the most likely leading edgetiming and the most likely trailing edge timing.

[0103] Let us suppose that the selected clock signal is a clock signalCLK_(x),

[0104] if k₁≧k₂ x=[(k₁+k₂+n)/2],

[0105] if k₁<k₂, x=[(k₁+k₂)/2],

[0106] where k₁ is the most likely leading edge timing, and k₂ is themost likely trailing edge timing, and [X] is the Gauss' notation, whichimplies the maximum integer that does not exceed X.

[0107] The clock selection circuit 5 selects one of the clock signalsCLK₀-CLk_(n−1) to output a clock selection signal 1 indicative of theselected clock signal CLK_(x) to the output circuit 6.

[0108] The output circuit 6 outputs the selected clock signal CLK_(x) asa selection clock signal f. Moreover, the output circuit 6 outputs oneof the sample signals b₀ to b_(n−1) as a data reproduction signal g onthe basis of the selection clock signal f. The data reproduction signalg is substantially identical to a signal generated by sampling the inputsignal a with the selected clock signal. That is, let us suppose thatthe selected clock is the clock signal CLK_(x). The output circuit 6outputs a sample signal b_(x) among the sample signals b₀ to b_(n−1), asthe data reproduction signal g. The data reproduction signal g is thesignal synchronous with the clock signal CLK_(x), in which the originalwaveform of the input signal a is reproduced.

[0109] As mentioned above, the apparatus in the embodiment generates theclock signal f synchronous with the input signal a. Moreover, theapparatus samples the input signal a on the basis of the clock signal f,and reproduces the waveform of the input signal a.

[0110] In this embodiment, the signal reproducing circuit 3 is operatedonly when the leading edge and the trailing edge are detected in theinput signal a. When the leading edge and the trailing edge are notdetected from the input signal a, the signal reproducing circuit 3 isnot operated. Thus, the consumption of the electric power is suppressedin the apparatus.

Second Embodiment

[0111]FIG. 9 shows an apparatus in a second embodiment according to thepresent invention. The configuration of the apparatus in the secondembodiment is identical to that of the apparatus in the first embodimentexcept for that the leading edge timing detector 2 ₁ and the trailingedge timing detector 2 ₂ are respectively replaced by a leading edgetiming detector 7 ₁ and a trailing edge timing detector 7 ₂.

[0112] The leading edge timing detector 7 ₁ detects the leading edgetiming of the input signal a to output leading edge timing detectionsignals c₀′-c_(n−1)′ indicative of the leading edge timing of the inputsignal a.

[0113] The leading edge timing detection signals c₀′-c_(n−1)′ outputtedby the leading edge timing detector 7 ₁ are different from the leadingedge timing signals c₀-c_(n−1) in the first embodiment. The leading edgetiming detection signals c₀′-c_(n−1)′ are kept unchanged unless theinput signal a rises from the Low level to the High level. That is, theleading edge timing detection signals c₀-c_(n−1) outputted by theleading edge timing detector 2 ₁ return back to the Low level insynchronization with the clock signals CLK₀-CLK_(n−1) when the inputsignal a returns back to the Low level. On the other hand, the states ofthe leading edge timing detection signals c₀′-c_(n−1)′ outputted by theleading edge timing detector 7 ₁ are not changed unless the leading edgeis detected from the input signal a. This increases the margin of theoperational timing of the signal reproducing circuit 3 for capturing andprocessing the leading edge timing detection signals c₀′-c_(n−1)′, andthereby stabilizes the operation of the signal reproducing circuit 3.

[0114]FIG. 10 shows the leading edge timing detector 7 ₁. The leadingedge timing detector 7 ₁ includes AND gates 71 ₀-71 _(n−1), D-flip-flops72 ₀-72 _(n−1), an OR gate 73, inverters 74 ₁, 74 ₂, D-flip-flops 75₀-75 _(n−1) and inverters 76 ₁, 76 ₂.

[0115] An inverse of the sample signal b_(i) and the sample signalb_(i+1), which are outputted by the sampling circuit 1, are inputted tothe AND gate 71 _(i). Here, i is the integer between 0 and n−1. Forexample, in a case of i=0, the sample signal b₁ and the inverse of thesample signal b₀ are inputted to the AND gate 71 ₀. It should beunderstood that the sample signal b_(n) means the sample signal b₀. Thatis, the sample signal b₀ and the inverse of the sample signal b_(n−1)are inputted to the AND gate 71 _(n−1). The outputs of the AND gates 71₀-71 _(n−1) are connected to data terminals D of the D-flip-flops 72₀-72 _(n−1), respectively.

[0116] The clock signals CLK₀-CLK_(n−1) are inputted to clock terminalsCLK of the D-flip-flops 72 ₀-72 _(n−1), respectively. The D-flip-flops72 ₀-72 _(n−1) respectively latch the outputs the AND gates 71 ₀-71_(n−1) in synchronization with the leading edge of the clock signalsCLK₀-CLK_(n−1) respectively.

[0117] Output terminals Q of the D-flip-flops 72 ₀-72 _(n−1) areconnected to inputs of the OR gate 73. An output of the OR gate 73 isconnected to an input of the inverter 74 ₁. An output of the inverter 74₁ is connected to an input of the inverter 74 ₂. An output of theinverter 74 ₂ is connected to clock terminals CLK of the D-flip-flops 75₀-75 _(n−1).

[0118] The inverters 74 ₁, 74 ₂ delay the signal outputted by the ORgate 73 by a certain delay time so that the D-flip-flops 75 ₀-75 _(n−1)latch the signals outputted from the output terminals Q of theD-flip-flops 72 ₀-72 _(n−1) at proper timings.

[0119] The data terminals D of the D-flip-flops 75 ₀-75 _(n−1) areconnected to the output terminals Q of the D-flip-flops 72 ₀-72 _(n−1),respectively. The D-flip-flops 75 ₀-75 _(n−1) output the leading edgetiming detection signals c₀, to c_(n−1), from the output terminals Q.

[0120] An output of the inverter 74 ₂ is connected to an input of theinverter 76 ₁. An output of the inverter 76 ₁ is connected to an inputof the inverter 76 ₂. An edge detection signal e₁′ is outputted from anoutput of the inverter 76 ₂.

[0121] The inverters 76 ₁, 76 ₂ delay the signal outputted from theinverter 74 ₂ by a certain delay time so that the signal reproducingcircuit 3 latches the leading edge timing detection signals c₀′-c_(n−1)′at proper timings.

[0122] The leading edge timing detection signals c₀′-c_(n−1)′, which isindicative of the leading edge timing of the input signal a, areoutputted to the signal reproducing circuit 3.

[0123] On the other hand, FIG. 11 shows the configuration of thetrailing edge timing detector 7 ₂. The trailing edge timing detector 7 ₂includes AND gates 81 ₀-81 _(n−1), D-flip-flops 82 ₀-82 _(n−1), an ORgate 83, inverters 84 ₁, 84 ₂, D-flip-flops 85 ₀-85 _(n−1) and inverters86 ₁, 86 ₂.

[0124] The trailing edge timing detector 7 ₂ has the configurationidentical to that of the leading edge timing detector 7 ₁ and carriesout the operation identical to the respectively except for that thetrailing edge timing detector 7 ₂ detects the trailing edge timing ofthe input signal a to generate the trailing edge timing signalsd₀′-d_(n−1)′ indicative of the trailing edge timing. The detailedexplanation of the trailing edge timing detector 7 ₂ is not provided inthe following.

[0125] In the apparatus in the second embodiment, the consumption of theelectric power is suppressed similarly to the apparatus in the firstembodiment. Moreover, the apparatus in the second embodiment is higherin operational stableness than the apparatus in the first embodiment.

[0126] As described, the present invention reduces the consumptiveelectric power of the apparatus that carries out the operation based onthe edge timing.

[0127] Also, the present invention stabilizes the operation of theapparatus that carries out the operation based on the edge timing.

[0128] Although the invention has been described in its preferred formwith a certain degree of particularity, it is understood that thepresent disclosure of the preferred form has been changed in the detailsof construction and the combination and arrangement of parts may beresorted to without departing from the spirit and the scope of theinvention as hereinafter claimed.

What is claimed is:
 1. An apparatus comprising: an edge detectingcircuit which detects edges of an input signal to generate an edgetiming representing signal representative of edge timings of said edges;a signal processing circuit responsive to said edge timing representingsignal, wherein said edge detection circuit outputs an enable signal toenable said signal processing circuit to operate when said edgedetection circuit finds one of said edges; said signal processingcircuit executes a signal processing of said edge timing representingsignal in response to said enable signal.
 2. The apparatus according toclaim 1, wherein said edge detecting circuit quantizes said edge timingsto represent said edge timings in said edge timing representing signal.3. The apparatus according to claim 1, wherein said enable signalconsists of rectangular pulses having a pulse width larger than apredetermined value.
 4. The apparatus according to claim 1, wherein saidedge detection circuit detects said edges in synchronization with aclock signal, and said pulse width is larger than a cycle of said clocksignal.
 5. The apparatus according to claim 1, wherein said edgedetection circuit generates said enable signal based on said edge timingrepresenting signal.
 6. The apparatus according to claim 1, wherein saidedge detection circuit changes a state of said edge timing representingsignal is changed only when said edge detection circuit detects saidedges.
 7. The apparatus according to claim 1, wherein said edgedetecting circuit includes: a plurality of sampling circuits each ofwhich is responsive to one of clock signals for sampling said inputsignal in synchronization with said one of said clock signals togenerate a sample signal, said clock signals having different phaseseach other, and an edge timing determining circuit generates said edgetiming representing signal based on said sample signals received fromsaid plurality of sampling circuits, said edge timing determiningcircuit determining said edge timings on the basis of whether or not twoof said sample signals indicate different values.
 8. A clock signalreproducing circuit comprising: an edge detecting circuit which detectsedges of an input signal to generate an edge timing representing signalrepresentative of edge timings of said edges; a clock signal outputtingcircuit responsive to said edge timing representing signal forgenerating another clock signal synchronized with said input signal,wherein said edge detection circuit outputs an enable signal to enablesaid clock signal outputting circuit to operate when said edge detectioncircuit finds one of said edges.
 9. The clock signal reproducing circuitaccording to claim 8, wherein said clock signal outputting circuitselects one of a plurality of clock signals having different phases eachother on the basis of said edge timing representing signal and outputsaid one of said plurality of clock signals as said another clocksignal.
 10. The clock signal reproducing circuit according to claim 8,wherein said edges have a present edge which is latest of said edges,and a past edge detected before said present edge, and said clock signaloutputting circuit includes: a memorizing circuit memorizing a past edgetiming of said past edge, said another clock signal is outputted on thebasis of edge timings of said present edge and said past edge.
 11. Asignal reproducing circuit comprising: an edge detecting circuit whichdetects edges of an input signal to generate an edge timing representingsignal representative of edge timings of said edges; a clock signaloutputting circuit responsive to said edge timing representing signalfor generating another clock signal synchronized with said input signal;and a reproduced signal outputting circuit sampling said input signalwith said another clock signal to output a reproduced signal, whereinsaid edge detection circuit outputs an enable signal to enable saidclock signal outputting circuit to operate when said edge detectioncircuit finds one of said edges.
 12. A method of operating an apparatuscomprising: detecting edges of an input signal; outputting an edgetiming representing signal representative of edge timings of said edges;outputting an enable signal when one of said edges is detected; andenabling a circuit to operate in response to said edge timingrepresenting signal.
 13. The method according to claim 12, wherein saidcircuit outputs a clock signal synchronized with said input signal onthe basis of said edge timings.